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Intel Developer Forum: Silicon Photonics boosts datacentre connectivity
Microsoft Azure datacentres increase connectivity to 100Gbps thanks to Silicon Photonics interconnect
Silicon Photonics, Intel’s long-awaited optical interconnect technology that aims to deliver higher bandwidth at lower cost for datacentre networks, is now available commercially.
The chipmaker also announced a new member of its Xeon Phi family of high-performance computing (HPC) chips, to be known as Knights Mill.
The second day of the Intel Developer Forum (IDF) in San Francisco kicked off with a greater focus on the datacentre, traditionally one of Intel’s key markets.
Diane Bryant, executive vice-president for Intel’s Data Center Group, said: “We are currently going through a period of ‘hyper innovation’ that was putting great stress on datacentres and their infrastructure, with emerging applications demanding ever-higher network bandwidth.
“Datacentre east-west traffic has been doubling every 12 months. Today, this is handled by fibre-optic connections, but this is expensive. It is estimated that 50% of total network cost in the datacentre is fibre.”
Silicon Photonics is intended to solve that problem, said Bryant. It cuts the cost of fibre connections by using Intel’s existing chip lithography technologies to manufacture both the semiconductor laser light source and the transceiver circuitry on a single piece of silicon.
The first transceiver modules offer speeds of 100Gbps for switch-to-switch optical interconnects. But Intel has a roadmap to up this to 400Gbps in future, through Silicon Photonics 100G PSM4 (Parallel Single Mode fibre 4-lane) and Silicon Photonics 100G CWDM4 (Coarse Wavelength Division Multiplexing 4-lane) products.
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One customer planning to deploy the technology is Microsoft, which said it would use it in its Azure datacentres to help cope with the burgeoning bandwidth requirements of its cloud services.
“Back in 2009, server bandwidth was a gigabit per second. This year, we’re seeing 15Gbps,” said Kushagra Vaid, general manager for hardware infrastructure in Microsoft’s cloud and enterprise division.
According to Vaid, the problem is that, as data rates scale from 10Gbps to 25Gbps and beyond, “we start to hit a brick wall”. Vaid said new technology is required to support continued growth.
Bryant also unveiled the next chip in Intel’s Xeon Phi family of HPC processors, codenamed Knights Mills, which is due to arrive in 2017. This follows on from official availability of the Knights Landing chip this June, which features up to 72 processor cores, 16GB of high-speed memory integrated inside the chip package for low latency access, and can be configured with up to 384GB of main memory.
Few details
Intel disclosed few details about the forthcoming chip. It will be able to run as a standalone processor in its own right, rather than a co-processor, and will include new optimisations for boosting applications such as machine learning and artificial intelligence, according to the firm.
“We have included new instructions into the Intel instruction set for variable-precision floating point, offering even higher precision and improved efficiency,” said Bryant.
The company expects that by 2020, there will be more servers running data analytics than any other workload. These data analytics applications would be able to take advantage of the new variable-precision floating point instructions.
One firm that is already using Xeon Phi to accelerate analytics workloads is Baidu, the web services firm styled as China’s answer to Google. It is using the technology to improve speech recognition algorithms.
Baidu said it was planning to build and operate public cloud services based around Xeon Phi, to make HPC facilities accessible to a broader range of developers.
